STA | ssg 跟ss corner 的區別——謬誤更正版

• 2020 年 3 月 13 日
• 筆記

因為原文有重大謬誤，更正後刪除重發，抱歉抱歉，感謝@dragonBaby糖糖 的更正。

有驢友在驢群里問ssg 跟ss corner 的區別是什麼？老胡發了一本書，裡面有兩橢圓一頁文字足以說明了該問題，老驢發揚一貫的雞賊風格，從網上搜羅一遍相關內容，雜糅到一起，發出來。

隨著製程發展，傳統STA 方法學的『經典』模型疲態盡顯，要想保證足夠高的良率，而又不過於悲觀，就得不斷地對原有模型進行修正，於是有了不同的OCV 模型，也有了更多的PVT corner 跟RC corner. 下圖羅列了不同製程點引進的『修正技術』。關於PVT 可回顧《巴山夜雨漲秋池，邀君共學PVT：STA之PVT》《綠蟻新醅酒，紅泥小火爐：STA之OCV》——ps: 如果時間可以倒流，一定不吟詩，要噁心死自己了！

要討論ssg corner, 需從製程偏差的分類入手，《論STA | SOCV / POCV 之 variation》論述過製程偏差分為systematic 跟non-systematic, 其中non-systematic 又分為global variation 跟local variation.

• Global variation: 由於製程偏移導致的die-to-die, wafer to wafer, lot to lot 之間偏差，如：同一個chip上所有管子的溝道長度都比典型值偏大或偏小。
• Local variation (within-die or intra-die): 同一晶片上不同管子受製程偏差影響不同< 註：on chip variation 之源>，如：同一晶片上有些管子的溝道長度偏小，而有些管子的溝道長度卻偏大。顯然，local variation 比 global variation 小。

從統計結果可知，在老製程中，由於local variation 非常小，所以在K 庫時會將local variation 跟global variation 全都考慮進去，STA 分析時用worst-case 模型，對應的corner 為 SS (slow nMOS-slow pMOS ) 和 FF ( fast nMOS-fast pMOS)，其中SS corner 只有early derate, FF corner 只有late derate。而在新製程下，local variation 顯著增加，如果再用worst-case 模型會過於悲觀，所以採用了新的統計學模型，在K 庫時只包含global variation，local variation 用「統計學OCV——SOCV / POCV 」 進行補償，對應的corner 就是ssg, ffg.

為了不再引入謬誤，抓兩段英文原文過來。

The problem is on-die variation. We can』t assume that if one transistor is faster than typical that the transistor it is driving is also faster. There are a number of reasons for this but one big one is that optical proximity correction (OPC) means that identical transistors do not end up identical on the mask since that depends on what is around them. In response, foundries have broken out on-die variation as a separate component in their SPICE models. They created global corners for slow, typical and fast. These global corners, called SSG (slow global), TTG (typical global) and FFG (fast global), only include between wafer variance. On-die variance is separated out as a set of local parameters as part of the SPICE model that work with Monte-Carlo (MC) SPICE around the global corners.

Figure 1.12 shows the relative impact of global (σgo) and local (σlo) variations in older and newer technologies. Global variations, also known as inter-die variations, present a radial dependence through the wafer and were successfully considered in the past using worst-case analysis . This was because the impact of local variations was significantly less severe than inter-die variations in older technologies. This is illustrated in Fig. 1.12a where the spread of the saturation current of nMOS and pMOS transistors due to local variations (3σlo) is much smaller than for global variations (3σgo). The final corners (FF and SS) are close to the corners without local variations (FFgo and SSgo). In older technologies, corner- based analysis could guarantee a good yield of a circuit after fabrication. However, local variations due to the nature of their statistical behavior are pessimistically modeled by worst-case analysis. This fact aggravates in newer technologies, which present significant local variations. Figure 1.12b shows that the relative impact of intra-die variations (3σlo) with respect to global variations (3σgo) increases significantly in newer technologies. Now, there is a significant difference between the final corners (FF and SS) and the corners without local variations (FFgo and SSgo). As a consequence, the cost incurred by corner-based design becomes even higher in newer technologies and shows the necessity of using statistical analysis in the design of current and future semiconductor technologies.

此外，順道澄清三個被反覆問到的問題：

• AOCV 或LVF 為什麼要考慮spatial derate? 老驢以為亦是為了模型修正，spatial derate 用於模擬Spatially correlated variations: 相較於距離相距較遠的管子，相鄰管子有像似特徵。這也是AOCV 跟 SOCV / POCV 要考慮 spatial / distance 的原因。
• PVT, 除了P 的variation 之外，V 跟T 的variation 怎麼設置？在較新製程的sign-off requirment 中，會有V/T 的variation table, 其中V 的index 是靜態IR-drop 的百分比，至於具體如何設，怎麼設，按照要求來！不逾矩！
• AOCV 或LVF 中只有cell 的variation, 是否需要設置net 的variation? 這裡通常會提到： front end of line (FEOL) 跟 back end of line (BEOL), 驢號之前論述過net 對應的RC corner, 可回顧《抽刀斷水水更流，RC Corner不再愁：STA之RC Corner》《一曲新詞酒一杯，RC Corner繼續飛: STA之RC Corner拾遺》《且將新火試新茶，深究趁年華：STA之RC Corner再論》，先進製程net 跟Via 在製造過程中也會有製程偏差，對於這部分製程偏差，sign-off requirment 中同樣會有張表，通常是7%。